Synchronization circuits are generally used to synchronize the internal clocks of multiple devices within a distributed system. For example, a system may have multiple switching power supplies. In such a system, external frequency synchronization is used to set the power supply switching noise at a frequency where system interference can be avoided. External frequency synchronization is also used to reduce the ripple current, and is also used to eliminate beat frequencies resulting from switching regulators operating at different frequencies.
Switching power supplies may need to operate using an external clock signal when one is available, but may also need to operate using an internal clock when no external clock is available. For example, shortly after power-on, power supplies may be operational before clock circuitry becomes operational, so a switching regulator needs to be able to operate from an internal oscillator until an external clock signal is available. Also, during a standby mode, external clocks may be turned off, but the power supplies may need to maintain standby power. It is common for switching regulators to have a clock terminal (sometimes labeled RT/CLK) and the switching regulators can switch between an external clock and an internal clock depending on the state of the clock terminal. If the RT/CLK terminal is held to a low or high voltage, the switching regulator uses an internal clock generator having a frequency determined by an internal resistor. If the RT/CLK terminal is driven with an external resistor, the switching regulator uses an internal clock generator having a frequency determined by the external resistor. If the RT/CLK terminal is raised to a voltage above a predetermined threshold and driven with an appropriate external clock signal, then the switching regulator synchronizes its internal clock to the external clock signal.
For switching regulators using Pulse-Width-Modulation (PWM), a pulse controls the time during which an inductor is energized within each switch period. Typically, PWM regulators have a closed-loop feedback system. For peak current mode PWM, if the duty cycle of the PWM pulses becomes greater than 50 percent, the closed-loop feedback system may cause the PWM pulses to alternate between two values of duty cycle with an average duty cycle of 50 percent, so there is no convergence to a steady-state pulse width. This is called sub-harmonic oscillation. To prevent sub-harmonic oscillation, it is common to modify the rate-of-change (slope) of the feedback control signal as a function of pulse width and as a function of switching frequency.
FIG. 1 illustrates an example prior art power supply 100. The power supply 100 includes a switching regulator 102 that drives an external inductor 104 and an external capacitor 106. The switching regulator 102 includes a PWM circuit 108 that controls switches 110 and 112. The duty cycle of switch 110 determines the time that the inductor 104 is energized within each switch period. The switching regulator 102 also includes a synchronization circuit 114. The switching regulator 102 also includes a RT/CLK terminal 116, which may be coupled to an external clock signal 118 through a tri-state buffer 120. If there is no external clock signal 118, then the tri-state buffer 120 is in a high-impedance state, and an amplifier 122 drives the voltage at the RT/CLK terminal 116 to a reference voltage VREF. The resulting current through an external resistor 124 controls the frequency of a local oscillator 126. If the RT/CLK terminal 116 is forced by the external clock 118, then the tri-state buffer 120 is in a low-impedance state, in which case the amplifier 122 and an electronic switch 128 are turned off, and the frequency of the local oscillator 126 is controlled by a Phase-Locked-Loop (PLL) 130. As a result, the output of the local oscillator 126 is synchronized to the external clock signal 118.
It is common for switching regulators to use a PLL (as illustrated in FIG. 1, 130) as part of a synchronization circuit to synchronize an internal clock to an external clock. In addition, it is common for peak-current-controlled switching regulators to use the frequency information in the form of current to control slope-compensation to prevent sub-harmonic oscillation. For example, the switching regulator 102 also includes a current control signal 132 that is provided to a slope-compensation circuit 134. The current control signal 132 is driven by the PLL 130 and by the electronic switch 128. When either the PLL 130 or the electronic switch 128 stops driving, the other takes over.
A switching regulator may be required to operate over a broad range of switching frequencies (for example, 100 KHz to 3 MHz). PLL's require a relatively large area on an integrated circuit die, and the size and cost of PLL's increase as the required range of frequencies increases. PLL's also require a finite amount of time to stabilize after a transition from internal clock mode to external clock mode and from external clock mode to internal clock mode. This stabilization time can cause a voltage regulator to lose its control over the regulation of its output voltage. There is a need for synchronization circuits with lower cost and smaller die area, while still providing the functions of synchronization to an external clock and extracting frequency information from the clock for use in slope-compensation. In addition, there is a need to minimize perturbations to the internal clock frequency and the slope-compensation control current during a transition from an external clock mode to an internal clock mode and during a transition from an internal clock mode to an external clock mode.